HIGH-SPEED PCB LAYOUT / 04
CPU PCIe Gen5 Device Down Topology
Via-stub control, interleaved routing and reference-plane planning for a CPU-to-device channel.
Topology notes
The following routing constraints are supplied for this design example and should be applied with the relevant platform design guide and PCB stack-up.
- Maximum allowed vias
- 4
- Maximum via stub length
- 250 µm
- Maximum total routing length
- 190 mm
AC coupling capacitors
A nominal value of 220 nF is recommended. The specified range is 176 nF to 265 nF, including tolerance.
Routing type
Main-route routing must be interleaved.
Reference-plane requirements
Microstrip
The reference plane must be continuous ground.
Dual stripline
Ground on both sides is strongly preferred. If necessary, one side may be a power plane with a low amount of low-frequency noise. The other side must be continuous ground, and that ground plane must be closer to the signal route.
Layout focus
The example illustrates differential routing organization within the device-down topology. Via count, stub length, total route length and reference-plane continuity are constraints to verify against the PCB design data and stack-up; the image is a layout illustration rather than an electrical compliance result.
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